ASIC & digital flows
OpenLaneBuilding end-to-end demos from Verilog to GDS with open-source tooling and validating blocks with KLayout + simulation.
Computer Engineering Student
Computer Engineering student with focus spanning ASIC design, AR optics, and ML, combining simulation, FPGA prototyping, and hands-on hardware builds.
Building end-to-end demos from Verilog to GDS with open-source tooling and validating blocks with KLayout + simulation.
Experimenting with heads-up displays for skiing and cycling, integrating sensors, weather data, and low-latency overlays.
Modeling upconversion and IR materials to map trade-offs for night vision and sensing applications.